The present invention relates to a cell bus arbitration system and method and more particularly but not exclusively to a cell bus arbitration system and method for use in conjunction with an ATM switch.
In a certain ATM switch layouts, the ATM switch requires external buffers to store data cells until the switch is prepared to handle these cells. These external storage buffers are controlled by cell buffer managers (CBM) which themselves are connected to a high speed data bus which is connected to the input of the ATM switch. A plurality of CBMs are used in order to ensure that there is a cell available at all times for the switch.
When the ATM switch requires a cell, one and only one of the CBMs is assigned mastery of the bus, allowing it to place one or more cells, from its external storage buffer, on the bus. The operation is high speed and it is necessary to ensure that a cell is placed promptly onto the bus when it is required, and that collisions on the bus between data from more than one CBM are avoided.
It is known to control the CBMs using a master controller. The master controller is able to provide an enable signal to each individual CBM and is operable to enable one CBM at a time. In order to ensure safe operation the master controller is generally duplicated and further control has to be provided to determine which master controller is active at any given time.
The above arrangement leads to relatively high system overhead in hardware terms, with two separate controllers operating a number of CBM""s.
According to a first aspect of the present invention there is provided a cell bus arbitration system comprising a data bus and a plurality of modules operative for sending data in data cells, the modules being connectable to the data bus and each one of the plurality of modules being in communication with each one of the other modules via at least one control line such that each one of the plurality of modules is capable of receiving control signals generated by each one of the other modules, and wherein arbitration logic is operative to assign bus mastery to one of the plurality of modules. Preferably the data bus is connectable to the input of an ATM switch.
In a preferred embodiment each module is operative to exert a request for output when it has at least one cell to send, and bus mastery is assignable in turn to those modules asserting the request for output. Preferably, each module, upon being assigned bus mastery, is operative to relinquish bus mastery at the earlier of when it has no more cells to send and when a predetermined maximum time is reached. Again, preferably each module is operable to assert an output signal just prior to relinquishing mastery of the bus.
In an embodiment each module is adapted to determine from the arbitration logic which of the plurality of modules is to be assigned bus mastery.
A preferred embodiment comprises a deadlock prevention mechanism having a timer for each module set to a predetermined threshold time, and in which each module is set to assert bus mastery when the threshold time is reached without regard to the arbitration logic. Preferably a different threshold time is set for each module.
In an embodiment a predetermined threshold time, exceeding the maximum time required to give bus mastery to each module in turn, is set for each module and each module is operable to report an error state if the predetermined threshold time is reached whilst the module has data to send and bus mastery is not assigned to the module.
In accordance with an embodiment, the system is operable to detect whether bus mastery is being asserted by more than one module at any given time, and to place the more than one module asserting bus mastery into a waiting state.
In accordance with a second aspect of the present invention there is provided a cell buffer arbitration module for use with a cell buffer manager, the cell buffer manager module being connectable to a databus and being in communication with each one of a plurality of other modules via at least one control line such that at least one control signal from itself and from each other module is receivable at the module, and in which arbitration logic is operative to assign bus mastery to one of the plurality of cell buffer manager modules.
In accordance with a third aspect of the present invention there is provided a bus arbitration method for a plurality of modules for sending data cells via a data bus, the method comprising
sending a first control signal from each module having a cell to send, to each one of the plurality of modules, and
arbitrating bus mastery between the plurality of modules at each module such that each module sending the First control signal is given a turn successively at mastery of the data bus.
Preferably the data bus is connected to the input of an ATM switch.
In an embodiment each module upon being assigned bus mastery, relinquishes bus mastery at the earlier of when it has no more cells to send and when a predetermined maximum time is reached.
Preferably each module is operable to assert a second control signal upon relinquishing mastery of the bus.
In a further preferred embodiment of the present invention each module determines, using internal arbitration logic, and after receipt of the second control signal, which of the plurality of modules is to be assigned bus mastery.
A preferred embodiment further comprises deadlock prevention in which each module is assigned a predetermined threshold time, and each module is preferably set to assert bus mastery when the threshold time is reached without a reassignment of bus mastery. Preferably a different threshold time is assigned to each module.
In another embodiment a predetermined threshold time, exceeding the maximum time required to give bus mastery to each module in turn, is set for each module and each module reports an error state if the predetermined threshold time is reached whilst the module has data to send and bus mastery is not yet received by the module.
Another embodiment of the method further comprises the step of monitoring to determine whether bus mastery is being asserted by more than one module at any given time, and, if such a multiple bus mastery assertion is detected then it places all modules asserting bus mastery into a waiting state.